Mithro Runs Down Open Source FPGA Toolchains

Tim [Mithro] Ansell has a lot to tell you about the current state of open FPGA tooling: 115 slides in 25 minutes if you’re counting. His SymbiFlow project aims to be the GCC of FPGA toolchains: cross-platform, multi-platform, completely free, and all-encompassing. That means that it’s an umbrella framework for …read more

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Open Source IDE for FPGAs as QtCreator Learns Verilog

Classic battles: PC vs Mac, Emacs vs Vi, Tastes Great vs Less Filling, and certainly one that we debate around the Hackaday watercooler: command line or IDE? There’s something to be said for using good old command line tools, and even if you like to configure your favorite editor to be nearly an IDE, at least it is one you are familiar with and presumably leverage over several different uses.

Most commercial FPGA tools come with a heavy-weight IDE. The open source tools for Lattice (IceStorm) typically is driven by the command line or a makefile. Until now. [Rochus-Keller] released …read more

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Icestorm Tools Roundup: Open Source FPGA Dev Guide

We like the ICE40 FPGA from Lattice for two reasons: there are cheap development boards like the Icestick available for it and there are open source tools. We’ve based several tutorials on the Icestorm toolchain and it works quite well. However, the open source tools don’t always expose everything that you see from commercial tools. You sometimes have to dig a little to find the right tool or option.

Sometimes that’s a good thing. I don’t need to learn yet another fancy IDE and we have plenty of good simulation tools, so why reinvent the wheel? However, if you are …read more

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Visualizing Verilog Simulation

You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation. You might get some printed information or you might get a graphical result by dumping a waveform, but you don’t usually see the circuit. A new site combines Yosys and a Javascript-based logic simulator to let you visualize and simulate Verilog in your browser. It is a work in progress on GitHub, so you might find a few hiccups like we did, but it is still an …read more

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