Category Archives: verilog

FPGA Testbenches Made Easier

Posted on by

You finally finish writing the Verilog for that amazing new DSP function that will revolutionize human society and make you rich. Does it work? Your first instinct, of course, is to blow it into your FPGA of choice and see if it works. If it does, that was a great idea. If it doesn’t, it was a terrible idea because — typically — it is hard to look inside the FPGA. That’s why you’ll typical simulate your logic on a desktop computer before you commit it to the FPGA. But that means you have to delay gratification long enough to …read more

Continue reading FPGA Testbenches Made Easier→

X-Ray Vision for FPGAs: Using Verifla

Posted on by

Last time I talked about how I took the open source Verifla logic analyzer and modified it to have some extra features. As promised, this time I want to show it in action, so you can incorporate it into your own designs. The original code didn’t actually capture your data. Instead, it created a Verilog simulation that would produce identical outputs to your FPGA. If you were trying to do some black box simulation, that probably makes sense. I just wanted to view data, so I created a simple C program that generates a VCD file you can read with …read more

Continue reading X-Ray Vision for FPGAs: Using Verifla→

Hands on with the Arduino FPGA

Posted on by

All of the tools you need to work with the FPGA Arduino — the Vidor — are now in the wild!

We reported earlier that a series of French blog posts finally showed how all the pieces fit together to program the FPGA on the Arduino MKR4000 Vidor board. Of course, I wasn’t content to just read the Google translation, I had to break out the board and try myself.

I created a very simple starter template, a tool in C to do the bitstream conversion, required, and bundled it all together in one place. Here’s how you can use …read more

Continue reading Hands on with the Arduino FPGA→

Logic Analyzers for FPGAs: A Verilog Odyssey

Posted on by

Sometimes you start something simple and then it just leads to a chain reaction of things. I wanted to write a post about doing state machines in Verilog and target the Lattice iCEstick board that we often use for quick FPGA projects. That led to a small problem: how do you show what’s going on inside? In this series of posts, we’ll look at building a logic analyzer into an FPGA to help debug itself, instantiating memory, and — finally — state machines.

Logic analysis is a common tool in FPGA development. If you use Altera, they have Signal Tap …read more

Continue reading Logic Analyzers for FPGAs: A Verilog Odyssey→

iCEstick Makes Terrible Radio Transmitter

Posted on by

We’ve done a lot of posts on how to use the Lattice iCEstick ranging from FPGA tutorials to how to use one as a logic analyzer. If you picked up one of these inexpensive boards here’s a fun little experiment. [T4D10N] saw a project [Hamster] put together to send SOS on the FM radio band using nothing but an FPGA. [Hamster used a Spartan], so he decided to do the same trick using an iCEstick with the open source IceStorm tools.

You might be surprised that the whole thing only takes 53 lines of Verilog — less if you cut …read more

Continue reading iCEstick Makes Terrible Radio Transmitter→

Learn Verilog In Your Browser

Posted on by

We are big fans of tools in the browser for education. You have a consistent environment maintained by someone else, you don’t have to install anything, and you can work from any computer you happen to find yourself. The HDLBits site has a great set of Verilog “exams” that would be a big help to anyone trying to learn or brush up on their Verilog skills.

The site offers a range of topics that go from the silly (output a constant 1 or 0) to full-blown state machines and testbenches. The site isn’t tutorial in nature, instead it offers a …read more

Continue reading Learn Verilog In Your Browser→

How to Add UART to Your FPGA Projects

Posted on by

Being able to communicate between a host computer and a project is often a key requirement, and for FPGA projects that is easily done by adding a submodule like a UART. A Universal Asynchronous Receiver-Transmitter is the hardware that facilitates communications with a serial port, so you can send commands from a computer and get messages in return.

Last week I wrote about an example POV project that’s a good example for learn. It was both non-trivial and used the board’s features nicely. But it has the message hard coded into the Verilog which means you need to rebuild the …read more

Continue reading How to Add UART to Your FPGA Projects→

Visualizing Verilog Simulation

Posted on by

You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation. You might get some printed information or you might get a graphical result by dumping a waveform, but you don’t usually see the circuit. A new site combines Yosys and a Javascript-based logic simulator to let you visualize and simulate Verilog in your browser. It is a work in progress on GitHub, so you might find a few hiccups like we did, but it is still an …read more

Continue reading Visualizing Verilog Simulation→

Learn FPGA with this Persistence of Vision Hack

Posted on by

Everybody wants to give FPGA development a try and here’s a great way to get into it. You can build your own Persistence of Vision display using a $30 dev board. It’s a fun project, and you’ll learn quite a bit about designing for an FPGA, as well as using the Quartus design software.

The inspiration for this article comes from [vpecanins] who did an example project where you wave the board back and forth and a message appears in mid air. This uses the MAX1000, a pretty powerful yet odd FPGA board for about $30. It contains an Intel …read more

Continue reading Learn FPGA with this Persistence of Vision Hack→

Getting Good at FPGAs: Real World Pipelining

Posted on by

Parallelism is your friend when working with FPGAs. In fact, it’s often the biggest benefit of choosing an FPGA. The dragons hiding in programmable logic usually involve timing — chaining together numerous logic gates certainly affects clock timing. Earlier, I looked at how to split up logic to take better advantage of parallelism inside an FPGA. Now I’m going to walk through a practical example by modeling some functions. Using Verilog with some fake delays we can show how it all works. You should follow along with a Verilog simulator, I’m using EDAPlayground which runs in your browser. The code …read more

Continue reading Getting Good at FPGAs: Real World Pipelining→