Category Archives: verilog

Pipelining Digital Logic in FPGAs

Posted on by

When you first learn about digital logic, it probably seems like it is easy. You learn about AND and OR gates and figure that’s not very hard. However, going from a few basic gates to something like a CPU or another complex system is a whole different story. It is like going from “Hello World!” to writing an operating system. There’s a lot to understand before you can make that leap. In this set of articles, I want to talk about a way to organize more complex FPGA designs like CPUs using a technique called pipelining.

These days a complex …read more

Continue reading Pipelining Digital Logic in FPGAs→

Forth System-On-Chip Takes Us Back to the 80s

Posted on by

For anyone who has dealt with the programming language Forth, odds are good that you picked it up back in the 80s. Since the language is still in use for many applications, though, you might not have this sort of nostalgic feeling for the language that some might have. For that, though, you might want to try out [Richard]’s implementation which simulates the microcomputers of the 80s using this unique language.

The system has an FPGA-based CPU written in Verilog. It runs on a Nexys-3 board and features PS/2 Keyboard input, a VGA output with a VHDL VT100 terminal emulation …read more

Continue reading Forth System-On-Chip Takes Us Back to the 80s→

Learn FPGA Programming from the 1940s

Posted on by

We often think that not enough people are building things with FPGAs. We also love the retrotechtacular posts on old computer hardware. So it was hard to pass up [karlwoodward’s] post about the Chip Hack EDSAC Challenge — part of the 2017 Wuthering Bytes festival.

You might recognize EDSAC as what was arguably the first operational computer if you define a computer as what we think of today as a computer. [Maurice Wilkes] and his team invented a lot of things we take for granted today including subroutines (Wheeler jumps named after a graduate student).

The point to the EDSAC …read more

Continue reading Learn FPGA Programming from the 1940s→

FPGA Clocks for Software Developers (or Anyone)

Posted on by

It used to be that designing hardware required schematics and designing software required code. Sure, a lot of people could jump back and forth, but it was clearly a different discipline. Today, a lot of substantial digital design occurs using a hardware description language (HDL) like Verilog or VHDL. These look like software, but as we’ve pointed out many times, it isn’t really the same. [Zipcpu] has a really clear blog post that explains how it is different and why.

[Zipcpu] notes something we’ve seen all too often on the web. Some neophytes will write sequential code using Verilog or …read more

Continue reading FPGA Clocks for Software Developers (or Anyone)→

FPGA Clocks for Software Developers (or Anyone)

Posted on by

It used to be that designing hardware required schematics and designing software required code. Sure, a lot of people could jump back and forth, but it was clearly a different discipline. Today, a lot of substantial digital design occurs using a hardware description language (HDL) like Verilog or VHDL. These look like software, but as we’ve pointed out many times, it isn’t really the same. [Zipcpu] has a really clear blog post that explains how it is different and why.

[Zipcpu] notes something we’ve seen all too often on the web. Some neophytes will write sequential code using Verilog or …read more

Continue reading FPGA Clocks for Software Developers (or Anyone)→

VexRiscv: A Modular RISC-V Implementation for FPGA

Posted on by

Since an FPGA is just a sea of digital logic components on a chip, it isn’t uncommon to build a CPU using at least part of the FPGA’s circuitry. VexRiscv is an implementation of the RISC-V CPU architecture using a language called SpinalHDL.

SpinalHDL is a high-level language conceptually similar to Verilog or VHDL and can compile to Verilog or VHDL, so it should be compatible with most tool chains. VexRiscv shows off well in this project since it is very modular. You can add instructions, an MMU, JTAG debugging, caches and more.

When you build a CPU in FPGA, …read more

Continue reading VexRiscv: A Modular RISC-V Implementation for FPGA→

Simulating the Learn-by-Fixing CPU

Posted on by

Last time I looked at a simple 16-bit RISC processor aimed at students. It needed a little help on documentation and had a missing file, but I managed to get it to simulate using a free online tool called EDA Playground. This time, I’ll take you through the code details and how to run the simulation.

You’ll want to refer to the previous post if you didn’t read it already. The diagrams and tables give a high-level overview that will help you understand the files discussed in this post.

If you wanted to actually program this on a real FPGA, …read more

Continue reading Simulating the Learn-by-Fixing CPU→

Learn by Fixing: Another Verilog CPU

Posted on by

Because I often work with students, I’m always on the look-out for a simple CPU, preferably in Verilog, in the Goldilocks zone. That is, not too easy and not too hard. I had high hopes for this 16-bit RISC processor presented by [fpga4student], but without some extra work, it probably isn’t usable for its intended purpose.

The CPU itself is pretty simple and fits on a fairly long web page. However, the details about it are a bit sparse. This isn’t always a bad thing. You can offer students too much help. Then again, you can also offer too little. …read more

Continue reading Learn by Fixing: Another Verilog CPU→

Learn by Fixing: Another Verilog CPU

Posted on by

Because I often work with students, I’m always on the look-out for a simple CPU, preferably in Verilog, in the Goldilocks zone. That is, not too easy and not too hard. I had high hopes for this 16-bit RISC processor presented by [fpga4student], but without some extra work, it probably isn’t usable for its intended purpose.

The CPU itself is pretty simple and fits on a fairly long web page. However, the details about it are a bit sparse. This isn’t always a bad thing. You can offer students too much help. Then again, you can also offer too little. …read more

Continue reading Learn by Fixing: Another Verilog CPU→

FPGAs in C with Cynth

Posted on by

Programming an FPGA with Verilog looks a lot like programming. But it isn’t, at least not in the traditional sense. There have been several systems that aim to take C code and convert it into a hardware description language. One of these, cynth, is simple to use and available on GitHub. You will need to install scala and a build system called sbt, if you want to try it.

There are limitations, of course. If you want a preprocessor, you’ll have to run it separately. You can’t use global variables, multiplication, floats, and many other pieces of C. The compiler …read more

Continue reading FPGAs in C with Cynth→